A final project for CE232 course at University of Thessaly under the direction of Dr. Nikolaos Bellas. The project’s purpose was to design and simulate a MIPS(Microprocessor without Interlocked Pipeline Stages) pipelined Central Processing Unit(CPU) using the verilog hardware description language. The objectives of the project consisted of furthering our understanding of pipelining and processor design as well as providing well commented Verilog RTL source code, complete simulation test benches & scripts, and detailed documentation. and to further understand the MIPS instruction set.
1. 32-bit data width
2. classic 5-stage static pipeline, 1 branch delay slot, theoretical CPI is 1.0
3. pipeline is able to detect and prevent RAW hazards, no forwarding logic
4. 32 general purpose registers
5. supporting all R format, I format and J format instructions