Verilog HDL

I consider myself as an advanced Verilog Programmer who has completed successfully plenty of projects for both in academic and commercial purposes

Recently, (September-December 2014) me and my colleague, George Varvarelis completed a complete implementation of a 32bit MIPS CPU in Verilog. You can read the project description below:

A final project for CE232 course at University of Thessaly under the direction of Dr. Nikolaos Bellas. The project’s purpose was to design and simulate a MIPS(Microprocessor without Interlocked Pipeline Stages) pipelined Central Processing Unit(CPU) using the verilog hardware description language. The objectives of the project consisted of furthering our understanding of pipelining and processor design as well as providing well commented Verilog RTL source code, complete simulation test benches & scripts, and detailed documentation. and to further understand the MIPS instruction set.

---Technical brief---
1. 32-bit data width
2. classic 5-stage static pipeline, 1 branch delay slot, theoretical CPI is 1.0
3. pipeline is able to detect and prevent RAW hazards, no forwarding logic
4. 32 general purpose registers
5. supporting all R format, I format and J format instructions

University of Thessaly CE232 Teaching Assistant, Phd candidate George Floros Testimonial:

Dimitri and Georgios are one of the few project teams I have had this term, in CE232-Computer Organization and Design course, that could truly grasp and apply the concepts behind designing and simulating a MIPS microprocessor. The specifications of the the project involved understanding a pipeline architecture along with the forwarding, hazard and flushing units of the processor. The above ideas required to be proficient in the Verilog language in order to achieve the maximum score of the project. Dimitri's team excelled at the task. They came up with an efficient code which was easily readable and when assembled, the correct output from the processor was successfully achieved.

Comments are closed.